Sub-micron sized transistors are very well known and are used extensively in all types of electrical devices. It is also well known that these transistors often include deep source/drains and shallower source/drain extensions, that are located adjacent the gate electrodes of the transistors and between which a channel region is formed during an applied voltage. The source/drain extensions are typically formed by placing dopants into a semiconductor substrate through well known processes, such an implantation. The source/drain extensions are implanted immediately adjacent the gate electrodes and are ultimately intended to extend up to, if not slightly extend under, the gate electrode to reduce channel length.
The deeper source/drains, however, are offset from the gate electrodes. This is accomplished typically by using a spacer, which may also be referred to as, a sidewall spacer, an oxide spacer, or gate spacer. The spacer is formed by depositing a spacer layer over the gate electrodes in a deposition furnace, patterning, and etching the spacer layer to form an offset. Implantation processes are then used to implant deep source/drain dopants into the substrate. The spacer partially blocks the implantation of the dopants, and thus, offsets the deep source/drains from the gate electrodes.
Problems can arise, however, in that once implanted, the dopants that form the source/drain extensions are susceptible to moving within the substrate when subjected to high temperatures, such as the temperatures used to deposit the spacer layer. Thus, during the deposition of the spacer layer, the source/drain extension dopants are susceptible to some movement, which can affect channel length. If the movement is significant enough, it can negatively affect transistor performance, particularly as device sizes continue to shrink to 130 nm and below.